Non-integer frequency divider circuit

ABSTRACT

A non-integer frequency divider is disclosed. The non-integer frequency divider circuit includes several base stages connected to each other. The non-integer frequency divider circuit also includes a clocking circuit for passing an enable bit from one of the base stages to another such that only one of the base stages is enabled at any give time. The enable bit has a pulse width of one clock cycle. The outputs from the base stages are grouped together by an OR gate to generate a single output that is a fraction of an input clock signal.

BACKGROUND OF INVENTION

[0001] 1. Technical Field

[0002] The present invention relates to frequency divider circuits ingeneral, and in particular, to non-integer frequency divider circuits.Still more particularly, the present invention relates to a programmablenon-integer frequency divider circuit.

[0003] 2. Description of the Related Art

[0004] Frequency divider circuits are commonly employed in electronicdevices that include counting circuits, phase-locked loop circuits,and/or frequency synthesizer circuits. Generally speaking, frequencydividers are used to generate signals of relatively lower frequencies bydividing a high frequency signal already existed within an electronicsystem. For example, if a 50 MHz signal is desired from a 100 MHz clocksignal existed within an electronic system, a frequency divider is usedto divide the 100 MHz clock signal by two.

[0005] Due to the nature of digital logic, the easiest frequency dividercircuits to design are those that divide the frequency of an inputsignal by a factor of 2^(n) where n is an integer. These group offrequency divider circuits can divide an input clock frequency by 2, 4,8, 16, etc. In other words, these group of frequency divider circuitscan produce an output cycle for every 2, 4, 8, 16, etc. input cycles,respectively. More sophisticated frequency divider circuits that arecapable of dividing an input signal by all integer values, such as 2, 3,4, 5, etc., have been developed. But recently, it has become necessaryto have frequency divider circuits that is capable of dividing an inputsignal by non-integer values; that is, ones that can produce an outputcycle for every, for example, 2.5 or 3.25 input cycles.

[0006] The present disclosure describes a method for constructing aprogrammable non-integer frequency divider circuit with a desired rangeand resolution.

SUMMERY OF INVENTION

[0007] In accordance with a preferred embodiment of the presentinvention, a non-integer frequency divider circuit includes severalstages connected to each other. The non-integer frequency dividercircuit also includes a clocking circuit for passing an enable bit fromone of the stages to another such that only one of the stages is enabledat any give time. Preferably, the enable bit has a pulse width of oneclock cycle. The outputs from all the stages are grouped together by alogic gate, such as an OR gate, to generate a single output that is afraction of an input clock signal.

[0008] All objects, features, and advantages of the present inventionwill become apparent in the following detailed written description.

BRIEF DESCRIPTION OF DRAWINGS

[0009] The invention itself, as well as a preferred mode of use, furtherobjects, and advantages thereof, will best be understood by reference tothe following detailed description of an illustrative embodiment whenread in conjunction with the accompanying drawings, wherein:

[0010]FIG. 1 is a circuit diagram of a stage within a frequency dividercircuit, in accordance with a preferred embodiment of the presentinvention;

[0011]FIG. 2 is a circuit diagram of a frequency divider circuit havingonly one stage, in accordance with a preferred embodiment of the presentinvention;

[0012]FIG. 3 is a circuit diagram of a non-integer frequency dividercircuit having multiple stages, in accordance with a preferredembodiment of the present invention; and

[0013]FIG. 4 is a circuit diagram of a clock select circuit forproviding proper clocking to the non-integer frequency divide circuitfrom FIG. 3, in accordance with a preferred embodiment of the presentinvention.

DETAILED DESCRIPTION

[0014] In order to build a frequency divider circuit, the desired rangeand resolution of the frequency divider circuit are first specified.Range is defined as the maximum achievable divide mode, and resolutionis defined as the granularity of the divide mode within the range. Forexample, the available divide modes for a frequency divider circuithaving a range of 2 and a resolution of 0.125 are:

[0015] 1.000, 1.125, 1.250, 1.375, 1.500, 1.625, 1.750, 1.875, 2.000

[0016] As another example, the available divide modes for a frequencydivider having a range of 3 and a resolution of 0.25 are:

[0017] 1.00, 1.25, 1.50, 1.75, 2.00, 2.25, 2.50, 2.75, 3.00

[0018] The minimum divide mode is always 1. After the range andresolution have been defined, the number of stages needs to provide thedesired resolution is determined, as follows:

[0019] number of stages=1/resolution

[0020] Next, the number of latches in each stage of the frequencydivider circuit is determined, as follows:

[0021] number of latches=range

[0022] Because each stage requires an input clock; thus, the maximumnumber of input clocks equals the number of stages, as follows:

[0023] number of clocks=number of stages

[0024] All the input clocks have the same frequency but need to bephased-spaced from each other, and such phase spacing is equal to theresolution times clock cycle time, as follows:

[0025] phase spacing=resolution×clock cycle

[0026] Hence, the above-mentioned frequency divider circuit having arange of 2 and a resolution of 0.125, includes:

[0027] number of stages=1/0.125=8

[0028] number of latches=2

[0029] number of clocks=8

[0030] phase spacing=0.125 ×clock cycle=⅛ cycle

[0031] Similarly, the above-mentioned frequency divider circuit having arange of 3 and a resolution of 0.25, includes:

[0032] number of stages=1/0.25=4

[0033] number of latches=3

[0034] number of clocks =4

[0035] phase spacing=0.25×clock cycle=¼ cycle

[0036] Although each stage has an input clock, not all of the clocks areneeded for every divide mode. In addition, a particular stage may needdifferent clocks for different divide modes. A multiplexor network canbe used to steer the input clocks appropriately, and such multiplexornetwork will be further described in detail.

[0037] Referring now to the drawings, and in particular, to FIG. 1,there is depicted a circuit diagram of a stage for building a frequencydivider circuit, in accordance with a preferred embodiment of thepresent invention. As shown, a stage 10 includes a first latch 11, asecond latch 12, a multiplexor 13 and an AND gate 14. First latch 11 andsecond latch 12 are both clocked by a clock signal CLKIN. An output P30of first latch 11 is fed to an input A0 of second latch 12. Outputs P30and P40 of second latch 12 are fed to multiplexor 13. Multiplexor 13 iscontrolled by a control signal G0. Output P30 of first latch 11 andclock signal CLKIN are fed to AND gate 14.

[0038] The simplest frequency divider circuit that can be constructedwith only one stage, such as stage 10, is by feeding the output ofmultiplexor 13 back into an input A0 of first latch 11. With referencenow to FIG. 2, there is illustrated a circuit diagram of a frequencydivider circuit having only one stage, in accordance with a preferredembodiment of the present invention. As shown, a frequency dividercircuit 20 includes a first latch 21, a second latch 22, a multiplexor23 and an AND gate 24. First latch 21 and second latch 22 are bothclocked by a clock signal CLKIN. An output P30 of first latch 21 is fedto an input A0 of second latch 22. Outputs P30 and P40 of second latch22 are fed to multiplexor 23. Multiplexor 23 is controlled by a controlsignal G0. The output of multiplexor 23 is fed back into an input A0 offirst latch 21. Output P30 of first latch 21 and clock signal CLKIN arefed to AND gate 24 to generate a output signal CLKOUT.

[0039] Frequency divider circuit 20 operates as follows. When a RESETinput is pulsed, first latch 21 and second latch 22 are initialized tothe values of the signals at inputs of first latch 21 and second latch22. In the example shown in FIG. 2, first latch 21 is initialized to alogical high and second latch 22 is initialized to a logical low. Whencontrol signal G0 is low, output P30 of second latch 22 is fed back toinput A0 of first latch 21, and frequency divider circuit 20 essentiallybecomes a two-bit shift register. Since one of the bits is initializedhigh, the outputs of latches 21-22 are high at every other clock cycleCLKIN. Since output P30 of first latch 21 feeds one of the two inputs ofAND gate 24, AND gate 24 passes its other input, i.e., clock signalCLKIN, at every other clock cycle CLKIN. As such, output signals CLKOUTof frequency divider circuit 20 is a pulse train having a frequencyequal to the frequency of clock signal CLKIN divided by two. Because thewidth of the pulses of output signal CLKOUT is the same as that of clocksignal CLKIN, the duty cycle of output signal CLKOUT is not 50%.

[0040] When control signal G0 is high, output P40 of second latch 22 isfed back to input A0 of first latch 21. Output P40 reflects output P30of first latch 21; thus, when latches 21-22 are loading (versusreleasing), the signal at input A0 of first latch 21 passes through tooutput P40 of second latch 22. Of course, when latches 21-22 arereleasing, the data loaded into first latch 21 passes to second latch 22and out through P30 of second latch 22. In other words, when latches21-22 are loading, output P30 of first latch 21 passes through outputP40 of second latch 22 and back into input A0 of first latch 21. Suchconfiguration essentially functions as a one-bit shift register. Sincefirst latch 21 is initialized high, as mentioned previously, output P30of first latch 21 is always high and output signal CLKOUT passes everycycle of input clock signal CLKIN. As such, the output signal CLKOUT isthe input clock signal CLKIN divided by one.

[0041] In order to build a non-integer frequency divider circuit,several stages are “stitched” together to form a structure thatresembles a shift-register. Referring now to FIG. 3, there is depicted acircuit diagram of a non-integer frequency divider circuit havingmultiple stages, in accordance with a preferred embodiment of thepresent invention. As shown, a non-integer frequency divider circuit 30includes four stagesstage 1, stage 2, stage 3 and stage 4. Each stage,which includes a first latch, a second latch, a multiplexor and an ANDgate, is substantially identical to stage 10 from FIG. 1. For example,stage 1 includes a first latch 31 a, a second latch 32 a, a multiplexor33 a and an AND gate 34 a; stage 2 includes a first latch 31 b, a secondlatch 32 b, a multiplexor 33 b and an AND gate 34 b; stage 3 includes afirst latch 31 c, a second latch 32 c, a multiplexor 33 c and an ANDgate 34 c; and stage 4 includes a first latch 3 d, a second latch 32 d,a multiplexor 33 d and an AND gate 34 d. Stages 1-4 are clocked by CLKA,CLKB, CLKC, CLKD, respectively.

[0042] In addition, the output of multiplexor 33 a is fed to an input A0of first latch 31 b, the output of multiplexor 33 b is fed to an inputA0 of first latch 31 c, the output of multiplexor 33 c is fed to aninput A0 of first latch 31 d, and the output of multiplexor 33 d is fedto an input A0 of first latch 31 a. Multiplexors 33 a-33 d are commonlycontrolled by a control signal G0. The outputs from AND gates 34 a 34 dare fed to an OR gate 35 to produce a single output OUT.

[0043] During operation, a pulse having a pulse width of one clock cycleis passed from one stage to another within non-integer frequency dividercircuit 30. When such a pulse, or more appropriately known as an enablebit, is within a particular stage, it allows one cycle of thecorresponding input clock for that stage to pass to the output of thatstage. Consider stage 1 of non-integer frequency divider circuit 30.When first latch 31 a of stage 1 holds an enable bit and its output ishigh, AND gate 34 a is allowed to pass one cycle of the input clock forstage 1 to the output of stage 1. Second latch 32 a is used to delay thetransmission of the enable bit to stage 2 by 1 or ½ clock cycle,depending on which side of second latch 32 a is passed by multiplexor 33a (via control input G0).

[0044] In essence, when the first latch of a stage holds the enable bit,that stage is said to be “enabled” and, as stated, one cycle of thecorresponding input clock is passed to the output of that stage. Sincethe enable bit is only one clock cycle wide, only one stage can beenabled at a time. Thus, at any given time, only one stage is passing aninput clock pulse. In other words, at any given time, only one stageoutputs a logical high, and the remaining stages output a logical low.As such, the outputs from all the stages (such as outputs from AND gates34 a-34 d) can be combined via OR gate 35. The output of OR gate 35 is astring of pulses, each pulse derived from one of the four stages asdetermined by the location of the enable bit.

[0045] If non-integer frequency divider circuit 30 has a range of 2 anda resolution of 0.25, then 1/0.25=4 input clocks are required, eachphase spaced by a quarter (0.25) of a clock cycle. The phaserelationships between CLKA, CLKB, CLKC and CLKD vary, depending on thedivide value. CLKB can be a quarter cycle ahead of CLKA, a quarter cyclebehind, or even have the same phase. The phase relationships betweenCLKA, CLKB, CLKC and CLKD for each divide value is listed in Table I.TABLE I divide value 1 1.25 1.50 1.75 2.00 CLKA 0 0 0 0 0 CLKB 0 ¼{fraction (2/4)} ¾ 0 CLKC 0 {fraction (2/4)} {fraction (4/4)} (0){fraction (6/4)} ({fraction (2/4)}) 0 CLKD 0 ¾ {fraction (6/4)}({fraction (2/4)}) {fraction (9/4)} (¼) 0

[0046] In Table I, CLKA is considered the reference clock. The numbersin Table I indicate, for a particular clock, the spacing, in cyclesbetween that clock and CLKA. For a particular divide value, all theclocks are phase spaced by fixed amounts. For the divide-by-1 mode, thephase spacing is zero and all the clocks are in-phase. For thedivide-by-1.25 mode, the phase spacing is ¼ of a cycle. For thedivide-by-1.5 mode, the phase spacing is {fraction (2/4)} of a cycle.For each succeeding divide value, the spacing increases by ¼ of a cycle,which is also the resolution of non-integer frequency divider circuit30.

[0047] Appropriate clocks can be utilized to steer the correspondingstages in several ways, but the simplest is to utilize a clock selectcircuit that outputs the proper clocks based on control inputs thatreflect the desired divide mode. FIG. 4 illustrates such a clock selectcircuit.

[0048] With reference now to FIG. 4, there is illustrated a circuitdiagram of a clock select circuit for providing proper clocking tonon-integer frequency divide circuit 30, in accordance with a preferredembodiment of the present invention. As shown, a clock select circuit 40includes two levels of multiplexors. The first level includesmultiplexors 41 a-41 d. The second level includes multiplexors 42 a-42d. Multiplexors 41 a-41 d receives clock inputs CLKO, CLK1, CLK2 andCLK3, respectively. CLK1 is phase spaced ¼ of a cycle from CLKO, CLK2 isphased spaced {fraction (2/4)}of a cycle from CLKO, and CLK3 is phasedspace ⅓ of a cycle from CLKO. Multiplexors 42 a- 42 d outputs clockinputs CLKA, CLKB, CLKC and CLKD, respectively, for non-integerfrequency divider circuit 30 (from FIG. 3). Control signal S0 controlsmultiplexors 41 b and 42 c. Control signal S1 controls multiplexor 42 b.Control signal S2 controls multiplexor 42 d. The operations ofnon-integer frequency divider circuit 30 along with the outputs of clockselect circuit 40 are summarized in Table II. TABLE II S0 S1 S2 G0 CLKACLKB CLKC CLKD divide value 1 0 1 1 CLK0 CLK0 CLK0 CLK0 1.00 0 0 0 1CLK0 CLK1 CLK2 CLK3 1.25 1 1 0 0 CLK0 CLK2 CLK0 CLK2 1.50 0 1 1 0 CLK0CLK3 CLK2 CLK1 1.75 1 0 1 0 CLK0 CLK0 CLK0 CLK0 2.00

[0049] As has been described, the present invention provides a methodfor building a programmable non-integer frequency divider circuit. Theprogrammability refers to the ability of the frequency divider circuitbeing set, via control inputs, to a desired divide ratio by a user. Suchratio can be integer or non-integer values. A user can set the range andresolution of the divide values simply by adding or subtractingsubstantially identical stages either in hardware or through gatinglogic. As with integer-only frequency divider circuits, the divide valueof the non-integer frequency divider circuit of the present inventioncan be increased beyond two by increasing the number of latches inseries in each of the stages. For example, a user can set a non-integerfrequency divider circuit to a range of 3 and a resolution of 0.25,which allow divide values of 1.00, 1.25, 1.50, 1.75, 2.00, 2.25, 2.50,2.75, 3.00, by using four stages, each stage having three latches.Similarly, the user can also set a non-integer frequency divider circuitto a range of 4 and a resolution of 0.125, which allow divide values of1.000, 1.125, 1.250, 1.375, 1.500, 3.625, 3.750, 3.875, 4.000, by usingeight stages, each stage having four latches.

[0050] While the invention has been particularly shown and describedwith reference to a preferred embodiment, it will be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit and scope of the invention.

1. A frequency divider circuit comprising: a plurality of stagesconnected to each other; an enable bit having a pulse width of one clockcycle capable of being passed around said plurality of stages; aclocking circuit for passing said enable bit from one of said pluralityof stages to another such that only one of said plurality of stages isenabled at any give time; and a logic gate for coupling outputs fromsaid plurality of stages to generate an output signal that is a fractionof an input clock signal.
 2. The circuit of claim 1, wherein one of saidplurality of stages includes a first latch, a second latch, amultiplexor and a logic gate.
 3. The circuit of claim 2, wherein saidmultiplexor is a 2-1 multiplexor and said logic gate is an AND gate. 4.The circuit of claim 1, wherein said plurality of stages aresubstantially identical with each other.
 5. The circuit of claim 1,wherein said plurality of stages are connected to each other in a loopconfiguration.
 6. The circuit of claim 1, wherein the number of clocksin said clocking circuit equals to the number of said plurality ofstages.
 7. A method for building a frequency divider circuit, saidmethod comprising: defining a range and a resolution for said frequencydivider circuit; determining a number of stages in accordance with saidresolution; determining a number of latches in accordance with saidrange; determining a number of clocks in accordance with said number ofstages; connecting said number of stages to each other; providing anenable bit having a pulse width of one clock cycle capable of beingpassed around said stages; providing a clocking circuit for passing saidenable bit from one of said stages to another such that only one of saidstages is enabled at any give time; and coupling outputs from saidstages to generate an output signal that is a fraction of an input clocksignal.
 8. The method of claim 7, wherein said number of stages equals1/(said defined resolution).
 9. The method of claim 7, wherein saidnumber of latches equals said defined range.
 10. The method of claim 7,wherein said number of clocks equals said determined number of stages.11. The method of claim 10, wherein a phase spacing between said numberof clocks equals resolution x clock cycle.
 12. The method of claim 7,wherein one of said of stages includes a first latch, a second latch, amultiplexor and a logic gate.
 13. The method of claim 12, wherein saidmultiplexor is a 2-1 multiplexor and said logic gate is an AND gate. 14.The method of claim 7, wherein said stages are substantially identicalwith each other.
 15. The method of claim 7, wherein said method furtherincludes connecting said stages in a loop configuration.
 16. A stage forbuilding a frequency divider circuit, said stage comprising: a firstlatch; a second latch connected in series with said first latch; amultiplexor connected in series with said second latch; and a logic gatefor receiving an output from said first latch and a clock input signal.